參數(shù)資料
型號(hào)： MCIMX257DVM4
廠商： Freescale Semiconductor
文件頁數(shù)： 64/153頁
文件大?。?/td> 0K
描述： IC MPU I.MX25 COMM 400MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： i.MX25
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 128
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
RAM 容量： 144K x 8
電壓 - 電源 (Vcc/Vdd)： 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x12b
振蕩器型： 外部
工作溫度： -20°C ~ 70°C
封裝/外殼： 400-LFBGA
包裝： 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
18
Freescale Semiconductor
NOTE
This is to guarantee that POR is stable already at NVCC_CRM/QVDD
power domain interface before QVDD is turned on, and POR instantly
propagates to QVDD domain after QVDD is turned on.
4. Turn on other NVCCx digital I/O power supplies for not less than 1 ms and not more than 32 ms,
after QVDD reaches 90% of 1.2 V.
5. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC,
OSC24M_VDD, MPPLL_VDD, UPLL_VDD, and FUSEVDD (FUSEVDD is tied to GND if
fuses are not programmed) for not less than 1 ms and not more than 32 ms, after NVCCx reaches
90% of 3.3 V.
NOTE
This is to guarantee that analog peripherals can get properly initialized
(reset) values from QVDD domain and NVCCx domain.
6. Negate the POR signal for at least 90
μs after all previous steps.
NOTE
This is to guarantee that both POR logic and clocks are stable inside the
i.MX25 chip, before POR is removed.
The dV/dT should be no faster than 0.25 V/us for all power supplies, to
avoid triggering ESD circuit.
In addition, the following power-down sequence is recommended:
1. Turn off power for analog parts, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND
if fuses are not programmed).
2. Turn off QVDD.
3. Turn off NVCCx, PLL, OSC, and other powers.
NOTE
The power-down steps can be executed simultaneously, or very shortly one
after another.
3.3
Power Characteristics
Table 15 shows values representing maximum current numbers for the i.MX25 under worst case voltage
and temperature conditions. These values are derived from the i.MX25 with core clock speed up to
400 MHz. Additionally, no power saving techniques such as clock gating were implemented when
measuring these values. Common supplies are bundled according to the i.MX25 power-up sequence
requirements. Peak numbers are provided for system designers so that the i.MX25 power supply
requirements are satisfied during startup and transient conditions. Freescale recommends that system
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