i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
87
1 FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
3.7.9.2
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58 shows MII asynchronous input timings.
Table 65 describes the timing parameters (M10—M15)
shown in the figure.
Figure 58. MII Serial Management Channel Timing Diagram
Table 64. MII Asynchronous Inputs Signal Timing
ID
Characteristic
Min.
Max.
Unit
M91
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
Table 65. MII Serial Management Channel Timing
ID
Characteristic
Min.
Max.
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
0—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
—5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
M14
FEC_MDC pulse width high
40%
60%
FEC_MDC period
M15
FEC_MDC pulse width low
40%
60%
FEC_MDC period
FEC_MDC (output)
FEC_MDIO (output)
M14
M15
M10
M11
M12
M13
FEC_MDIO (input)