
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
53
3.7.4.2
Ungated Clock Mode Timing
Figure 22 shows the ungated clock mode timings of CSI, and
Table 42 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the VSYNC and PIXCLK signals are used, and the
HSYNC signal is ignored.
Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 41. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
CSI VSYNC to HSYNC time
tV2H
67.5
—
ns
P2
CSI HSYNC setup time
tHsu
1
—
ns
P3
CSI DATA setup time
tDsu
1
—
ns
P4
CSI DATA hold time
tDh
1.2
—
ns
P5
CSI pixel clock high time
tCLKh
10
—
ns
P6
CSI pixel clock low time
tCLKl
10
—
ns
P7
CSI pixel clock frequency
fCLK
—
48
± 10%
MHz
Table 42. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
CSI VSYNC to pixel clock time
tVSYNC
67.5
—
ns
P2
CSI DATA setup time
tDsu
1
—
ns
P3
CSI DATA hold time
tDh
1.2
—
ns
P4
CSI pixel clock high time
tCLKh
10
—
ns
P5
CSI pixel clock low time
tCLKl
10
—
ns
P6
CSI pixel clock frequency
fCLK
—
48
± 10%
MHz
PIXCLK
VSYNC
DATA[15:0]
P4
P1
P2
P3
P5
P6