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參數(shù)資料
型號: MCIMX258CJM4
廠商: Freescale Semiconductor
文件頁數(shù): 145/153頁
文件大?。?/td> 0K
描述: MPU IMX25 IND 400-MAPBGA
特色產(chǎn)品: MCIMX25 Applications Processors
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
91
3.7.11
Inter IC Communication (I2C) Timing
The I2C communication protocol consists of the following seven elements:
Start
Data source/recipient
Data direction
Slave acknowledge
Data
Data acknowledge
Stop
Figure 64 shows the timing of the I2C module. Table 69 and Table 70 describe the I2C module timing
parameters (IC1–IC6) shown in the figure.
Figure 64. I2C Module Timing Diagram
Table 69. I2C Module Timing Parameters: 3.0 V +/–0.30 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
IC1
I2CLK cycle time
10
-
2.5
μs
IC2
Hold time (repeated) START condition
4.0
-
0.6
-
μs
IC3
Set-up time for STOP condition
4.0
-
0.6
-
μs
IC4
Data hold time
01
3.452
01
0.92
μs
IC5
HIGH Period of I2CLK Clock
4.0
-
0.6
-
μs
IC6
LOW Period of the I2CLK Clock
4.7
-
1.3
-
μs
IC7
Set-up time for a repeated START condition
4.7
-
0.6
-
μs
IC8
Data set-up time
250
-
1003
-ns
IC9
Bus free time between a STOP and START condition
4.7
-
1.3
-
μs
IC10
Rise time of both I2DAT and I2CLK signals
-
1000
20+0.1Cb
4
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
-
300
20+0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
-
400
-
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
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