MCM62Y308
12
MOTOROLA FAST SRAM
loaded using the LDWREG instruction if a non–zero starting
address is desired. If 0000 was the first desired count, setting
up the Control Register to “clear” the Write counter is all that
is required (Bit 3 set to zero). A reload cycle using SAMPLE/
PRELOAD (WR preloaded low) and INTEST would also have
to be run in order to initialize the counter. While still in the
INTEST instruction at the Shift–DR state, the proper values of
WE and WR would then need to be preloaded for proper op-
eration of EZWRITE (WE high and WR high). After all this ini-
tializing is done, the EZWRITE instruction would be loaded
into the TAP instruction register in the Shift–IR state. When the
TAP controller is then moved to the Shift–DR state the EZWRI-
TE scan path would be inserted between TDI and TDO. This
scan path is composed of the 8 bit Data In register (see Table
5). The 8 bits to be written into the first address would be
scanned in (sampled values from the Data In pins would be
streaming out of TDO at the same time), then the TAP control-
ler would be moved to the Run–Test/Idle state where one cycle
of TCK would write the 8 bits into the address and increment
the counter. The TAP controller would then move back to the
Shift–DR state so that the next byte to be written can be serial-
ly loaded and the process would be repeated until all desired
bytes were written. During EZWRITE the Q0 – Q7 pins will be
in a High–Z state.
EZREAD TAP INSTRUCTION AND SCAN PATH
The EZREAD TAP instruction is provided to allow the user
to more easily and quickly read a large number of bytes from
the device serially through the TDO port. EZREAD shortens
the scan path for a serial read to just the 8 bit Data Out register
(see Table 6).
To serially read the device the following would occur: initial-
ization would be much like EZWRITE except that the Read Ad-
dress Counter should be reladed with the count BEFORE the
first one desired. So, if the first read needed to be address
0000 (and the counter is counting up), the Read Reload Regis-
ter would have to be preloaded with FFFF using the LDRREG
instruction. Again, SAMPLE/PRELOAD and INTEST instruc-
tions would need to be run to perform a reload cycle followed
by another Boundary–scan that set RE and RR high in antici-
pation of the EZREAD instruction. Also, WE should be set low
to prevent any unintended writes while reading. After this ini-
tializing, the EZREAD instruction would be loaded into the
TAP instruction register in the Shift–IR state. The TAP control-
ler would move to the Run–Test/Idle state where one cycle of
TCK would increment the counter, read the 8 bits from that ad-
dress, and load them into the Data Output register. The TAP
controller would then move to the Shift–DR state and the EZ-
READ scan path would be inserted between TDI and TDO.
This scan path is composed of the 8 bit Data Out register (see
Table 6). In the Shift–DR state the Data Out register would be
serially scanned out of the TDO port. This sequence through
the TAP state machine would then be repeated until all desired
bytes were read. EZREAD keeps the Q0 – Q7 pins active (if
G is preloaded low) to allow parallel reading of the data out if
desired.
EZREADZ TAP INSTRUCTION AND SCAN PATH
The EZREADZ TAP instruction behaves exactly like the
EZREAD instruction except that the all outputs are held in a
High–Z mode once the instruction is loaded.
DISABLING THE TEST ACCESS PORT AND
BOUNDARY SCAN
It is possible to use this device without utilizing the four pins
used for the IEEE 1149.1 Test Access Port. To circuit disable
the TAP controller without interfering with normal operation of
the device TCK must be tied to VSS to preclude midlevel in-
puts. Although TDI and TMS are designed in such a way that
an undriven input will produce a response identical to the ap-
plication of a logic 1, it is still advisable to tie these inputs to
VDD through a 1 k resistor. TDO should remain unconnected.
With the four Test Access Port pins disabled, the device can
only be used in its default power–up state. At power up, the de-
vice is configured to count up starting at address 0, the reload
pins (RR and WR) will clear the counters, the Expand ID bits
are set to 000, and the Output Enable pin (G) is configured as
an asynchronous input.