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參數(shù)資料
| 型號(hào)： | MCM62Y308J17 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| 中文描述： | 8K X 8 MULTI-PORT SRAM, 17 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大小： | 257K |
| 代理商： | MCM62Y308J17 |
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MCM62Y308
3
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
SOJ Pin Locations
Symbol
Type
Description
11
K
Input
CLOCK
– System clock input pin accepting a minimum 8 ns clock high
or clock low pulse at a minimum 20 ns clock cycle. All other
synchronous inputs excluding the test access port are captured on the
rising edge of this signal.
WRITE ENABLE
– Write enable is captured on K leading edge. When
asserted this causes the input data D0 – D7 to be written into the RAM
address controlled by the write address counter and increments the
counter for the next write.
READ ENABLE
– Read enable is captured on K leading edge. When
asserted increments the counter for the next read operation. This
causes a RAM read access from address controlled by the read
address counter to be inserted in the output register Q0 – Q7.
WRITE RELOAD
–
Write reload is captured on K leading edge. When
asserted this causes the write address counter to be initialized to the
contents of the write reload register or “cleared” as specified by control
register bit 3. See control register bit 3 for “cleared” description.
READ RELOAD
– Read reload is captured on K leading edge. When
asserted this causes the read address counter to be initialized to the
contents of the read reload register or “cleared” as specified by control
register bit 5. See control register bit 5 for “cleared” description.
OUTPUT ENABLE
– When asserted low causes the outputs Q0 – Q7
to become active and when deasserted high causes them to High–Z.
This pin can be either synchronous with K leading edge or
asynchronous as specified by control register bit 7.
DATA INPUT
– The levels on these pins are captured on the K leading
edge. The value captured will be written into the RAM if WE is also
asserted and the expand ID bits match the upper three bits of the write
address counter.
DATA OUTPUT
–
Data outputs are available from the read output
register < 15 ns from the rising edge of K when RE or RR is asserted.
outputs are disabled when the upper three bits of the read address
counter do not match the three expand ID bits of the control register.
G will also control the disabling of the outputs either synchronously or
asynchronously. See G description.
ROLL–OVER FLAG
–
These signals are asserted high on the clock
cycle where the address counters (write address counter for WRF and
read address counter for RRF) roll–over to 0000 during count down.
During count up these pins must be treated as don’t cares.
ROLL–OVER RESET
– The level on these pins is captured on the K
leading edge. When asserted low, each will reset their associated
roll–over flag output.
12
WE
Input
21
RE
Input
13
WR
Input
20
RR
Input
22
G
Input
9, 8, 7, 6, 5, 4, 3, 2
D0 – D7
Input
24, 25, 26, 27, 28, 29, 30, 31
Q0 – Q7
Output
17, 32
RRF, WRF
Output
16, 1
RRR, WRR
Input
TEST ACCESS PORT PIN DESCRIPTIONS
(The Test Access Port Conforms with the IEEE Standard 1149.1. It is also Used
to Load Device Specific Registers Used to Configure the MCM62Y308.)
SOJ Pin Locations
Symbol
Type
Description
15
TCK
Input
TEST CLOCK
– Samples and clocks all TAP events. All inputs are
captured on TCK rising edge and all outputs propagate from TCK falling
edge. It also can take the place of K in device operation in certain test
conditions.
TEST MODE SELECT
– Sampled on the rising edge of TCK.
Determines the movement through the TAP state machine (Figure 2).
This circuit is designed in such a way that an undriven input will
produce a response identical to the application of a logic 1.
TEST DATA IN
– Sampled on the rising edge of TCK. This is the input
side of the serial register placed between TDI and TDO. The register
placed between TDI and TDO is determined by the state of the TAP
state machine and what instruction is active in the TAP instruction
register. This circuit is designed in such a way that an undriven input
will produce a response identical to the application of a logic 1.
TEST DATA OUT
– Output that is active depending on the state of the
TAP state machine. Output changes off the trailing edge of TCK. This is
the output side of the serial register placed between TDI and TDO.
18
TMS
Input
14
TDI
Input
19
TDO
Output
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