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參數(shù)資料
| 型號： | MCM62Y308J17 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| 中文描述： | 8K X 8 MULTI-PORT SRAM, 17 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 257K |
| 代理商： | MCM62Y308J17 |
MCM62Y308
9
MOTOROLA FAST SRAM
TEST ACCESS PORT DESCRIPTIONS
INSTRUCTION SET
A four pin IEEE Standard 1149.1 Test Port (JTAG) is inclu-
ded on this device. There are two classes of instructions; stan-
dard instructions as defined in the IEEE 1149.1 standard and
device specific, or public, instructions that are used to control
the functionality of the device. When the TAP (Test Access
Port) controller is in the Shift–IR state the Instruction Register
is placed between TDI and TDO, least significant bit closest
to TDO. In this state the desired instruction would be serially
loaded through the TDI input (while the previous instruction
would be shifted out of TDO). The TAP instruction set for this
device is listed in Table 1.
TAP STANDARD INSTRUCTION SET
NOTE: The descriptions in this section are not intended to
be used without the supporting IEEE 1149.1–1993 Standard.
SAMPLE/PRELOAD TAP INSTRUCTION
The SAMPLE/PRELOAD TAP instuction is used to allow
scanning of the boudary–scan register without causing inter-
ference to the normal operation of the chip logic. The 26 bit
boundary scan register contains bits for all device signal and
clock pins and associated control signals (Table 2). This regis-
ter is accessible when the SAMPLE/PRELOAD TAP instruc-
tion is loaded into the TAP instruction register. When the TAP
controller is then moved to the Shift–DR state, the boundary
scan register is placed between TDI and TDO. This scan reg-
ister can then be used prior to the EXTEST instruction to pre-
load the output pins with desired values so that these pins will
drive the desired state when the EXTEST instruction is
loaded. It would be used prior to the INTEST instruction to pre-
load values into the input pins. As data is written into TDI, data
also streams out of TDO which can be used to pre–sample the
inputs and outputs. SAMPLE/PRELOAD would also be used
prior to the CLAMP instruction to preload the values on the
output pins that will be driven out when the CLAMP instruction
is loaded.
Table 2 shows the boundary–scan bit definitions. The first
column defines the bit’s ordinal position in the boundary–scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 0; the last bit to be shifted is 25.
The second column is the pin name and the third column is the
pin type.
EXTEST TAP INSTRUCTION
The EXTEST instruction is intended to be used in conjunc-
tion with the SAMPLE/PRELOAD instruction to assist in test-
ing
board
level
connectivity.
SAMPLE/PRELOAD instruction would be used to preload all
output pins (i.e., Q0 – Q7, RRF, and WRF). The EXTEST
instruction would then be loaded. During EXTEST the bound-
ary–scan register is placed between TDI and TDO in the Shift–
DR state of the TAP controller. Once the EXTEST instruction
is loaded, the TAP controller would then be moved to the Run–
Test/Idle state. In this state one cycle of TCK would cause the
preloaded data on the ouput pins to be driven while the values
on the input pins would be sampled (Q0 – Q7 will be active only
if G is preloaded with a zero; the value of the expand ID bits
is ignored). Note that TCK, not the Clock pin, K, is used as the
clock input while K is only sampled during EXTEST. After one
clock cycle of TCK, the TAP controller would then be moved
to the Shift–DR state where the sampled values would be
shifted out of TDO (and new values would be shifted in TDI).
These values would normally be compared to expected val-
ues to test for board connectivity.
Normally,
the
THE INTEST TAP INSTRUCTION
The INTEST instruction is intended to be used to assist in
testing internal device functionality. When the INTEST instruc-
tion is loaded the boundary–scan register is placed between
TDI and TDO in the Shift–DR state of the TAP controller (Table
2). While in the Shift–DR state, all input pins would be pre-
loaded via the boundary scan register to set up the desired
mode (i.e., read, write, reload, etc.). The TAP controller would
then be moved to the Run–Test/Idle state. In this state one or
more cycles of TCK would cause the preloaded data in the
boundary–scan register to be driven while the values of
Q0 – Q7 would be sampled (Q0 – Q7 will be active only if G
is preloaded with a zero, however the values of Q0 – Q7 will
Table 1. TAP Instruction Set
Instruction
Code
(Binary)
Description
Standard Instructions:
BYPASS
INTEST
SAMPLE/PRELOAD
EXTEST
HIGHZ
CLAMP
Device Specific (Public) Instructions:
LDRREG
LDWREG
LDBREG
LDCONT
RDCOUNT
EZWRITE
EZREAD
EZREADZ
*Default state at power–up.
1111*
0111
1100
0000
1010
1001
Bypass Instruction
Intest Instruction
Sample and/or Preload Instruction
Extest Instruction
High–Z all Output pins while bypass reg. is between TDI and TDO
Clamp Output pins while bypass reg. is between TDI and TDO
0001
0100
0101
0010
1000
0011
0110
1110
Load Read Address Reload Register
Load Write Address Reload Register
Load both Address Reload Registers (Write then Read)
Load Control Register
Read the values of the Read and Write Address Counters
Serial Write (using Write Address Counter)
Serial Read (using Read Address Counter)
Serial Read, outputs High–Z
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