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參數(shù)資料
| 型號： | MCM62Y308J17 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| 中文描述： | 8K X 8 MULTI-PORT SRAM, 17 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 257K |
| 代理商： | MCM62Y308J17 |
MCM62Y308
7
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 ns
1.5 V
. . . . . . . . . . . . . . .
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
50 Ohm Transmission Line
TAP CONTROLLER TIMING
MCM62Y308–17
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tCYC
tCKH
tCKL
tA
tCKZ
tCKX
tS
tSD
tH
tHD
30
—
ns
Clock High Time
12
—
ns
Clock Low Time
12
—
ns
Clock Low to Output Valid
5
9
ns
Clock Low to Output High–Z
0
9
ns
1
Clock Low to Output Active
0
9
ns
2, 3
Setup Time, Test Mode Select
2
—
ns
Setup Time, Test Data In
2
—
ns
Hold Time, Test Mode Select
2
—
ns
Hold Time, Test Data In
2
—
ns
NOTES:
1. Test Data Out will High–Z from a clock low edge depending on the current state of the TAP state machine.
2. Test Data Out is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine.
3. Transition is measured
±
500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
tA
tCKX
tCKZ
tHD
tSD
tCKH
tCKL
tS
tH
TAP CONTROLLER TIMING DIAGRAM
tCYC
TEST CLOCK
(TCK)
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
TEST DATA OUT
(TDO)
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| MCM6323ATS12R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
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