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參數(shù)資料
| 型號： | MCV14AI/SL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOIC-4 |
| 文件頁數(shù)： | 44/84頁 |
| 文件大小： | 1007K |
| 代理商： | MCV14AI/SL |
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2009 Microchip Technology Inc.
Preliminary
DS41338B-page 47
MCV14A
7.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, RBWUF)
The TO, PD and RBWUF bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
TABLE 7-7:
TO/PD/RBWUF STATUS
AFTER RESET
7.8
Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
7.8.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
RB3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.
7.8.2
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of
the following events:
1.
An external Reset input on RB3/MCLR/VPP pin,
when configured as MCLR.
2.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
3.
A change on input pin RB0, RB1, RB3 or RB4
when wake-up on change is enabled.
These events cause a device Reset. The TO, PD and
RBWUF bits can be used to determine the cause of
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The RBWUF bit indicates a change in state while in
Sleep at pins RB0, RB1, RB3 or RB4 (since the last file
or bit operation on RB port).
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
RBWUF
TO
PD
Reset Caused By
00
0
WDT wake-up from Sleep
00
u
WDT time-out (not from
Sleep)
01
0
MCLR wake-up from Sleep
01
1
Power-up
0u
u
MCLR not during Sleep
11
0
Wake-up from Sleep on pin
change
Legend: u = unchanged
Note 1:
The TO, PD and RBWUF bits maintain
their status (u) until a Reset occurs. A
low-pulse on the MCLR input does not
change the TO, PD and RBWUF Status
bits.
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Note:
Caution: Right before entering Sleep,
read the input pins. When in Sleep,
wake-up occurs when the values at the
pins change from the state they were in at
the last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
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