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參數(shù)資料
| 型號： | MCV14AI/SL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOIC-4 |
| 文件頁數(shù)： | 6/84頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | MCV14AI/SL |
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MCV14A
DS41338B-page 12
Preliminary
2009 Microchip Technology Inc.
3.2
Data Memory (SRAM and FSRs)
Data memory is composed of registers or bytes of
SRAM. Therefore, data memory for a device is
specified by its register file. The register file is divided
into two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling
desired operations of the MCV14A. See Figure 3-2 for
details.
The MCV14A register file is composed of 13 Special
Function Registers and 41 General Purpose Registers
3.2.1
GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 3.8 “Indirect Data Addressing:
3.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 3-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
FIGURE 3-2:
REGISTER FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
10h
Bank 0
Bank 1
Bank 2
Bank 3
3Fh
30h
20h
5Fh
50h
40h
7Fh
70h
60h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
PORTC
08h
Note 1:
Not a physical register. See Section 3.8 “Indirect Data Addressing: INDF and FSR Registers”.
FSR<6:5>
00
01
10
11
2Fh
4Fh
6Fh
0Dh
CM1CON0
CM2CON0
VRCON
09h
0Ah
0Bh
ADRES
ADCON0
0Ch
0Fh
INDF(1)
EECON
PCL
STATUS
FSR
EEDATA
EEADR
CM1CON0
CM2CON0
VRCON
ADRES
ADCON0
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
PORTC
VRCON
ADRES
ADCON0
INDF(1)
EECON
PCL
STATUS
FSR
EEDATA
EEADR
VRCON
ADRES
ADCON0
CM1CON0
CM2CON0
PORTC
Addresses map back to
addresses in Bank 0.
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