LOGIC COMMANDS AND REGISTERS MODE CONTROL R" />
參數(shù)資料
型號(hào): MCZ33742EG
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 43/71頁(yè)
文件大?。?/td> 0K
描述: IC SYSTEM BASIS CHIP CAN 28-SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)
電流 - 電源: 42mA
電源電壓: 5.5 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
產(chǎn)品目錄頁(yè)面: 808 (CN2011-ZH PDF)
Analog Integrated Circuit Device Data
48
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MODE CONTROL REGISTER (MCR)
Tables 16 through 18 describes the various Mode Control Registers.
Table 16. Mode Control Register
MCR
R/W
D3
D2
D1
D0
$000b
W
MCTR2
MCTR1
MCTR0
R
VDDTEMP
GFAIL
WDRST
Reset Value
0
Reset Condition (Write)(53)
POR, RESET
Notes
52.
BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.
53.
See Table 13 page 46, for definitions of reset conditions
Table 17. Mode Control Register Control Bits
MCTR
2
MCTR
1
MCTR
0
33742S Mode
Description
0
Enter/Exit Debug Mode
To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and
0
1
Normal
0
1
0
Standby
0
1
Stop, Watchdog OFF(54)
0
1
Stop, Watchdog ON(54)
1
0
1
0
1
Normal
No Watchdog running. Debug mode.
1
0
Standby
1
Stop
Notes
54.
Watchdog ON or OFF depends on RCR bit D3.
55.
Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be
previously set to logic [1].
Table 18. Mode Control Register Status Bits
Name
Logic
Description
BATFAIL
0
VSUP was not below VBF.
1
VSUP has been below VBF.
VDDTEMP
0
No over-temperature pre-warning.
1
Temperature pre-warning on VDD regulator (bit latched).
GFAIL
0
No failure.
1
CAN Failure or HS over-temperature or V2 low.
WDRST
0
No watchdog reset occurred.
1
Watchdog reset occurred.
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