LOGIC COMMANDS AND REGISTERS WAKE-UP REGIST" />
參數(shù)資料
型號(hào): MCZ33742EG
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 47/71頁(yè)
文件大小: 0K
描述: IC SYSTEM BASIS CHIP CAN 28-SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)
電流 - 電源: 42mA
電源電壓: 5.5 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
產(chǎn)品目錄頁(yè)面: 808 (CN2011-ZH PDF)
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
WAKE-UP REGISTER (WUR)
Tables 28 through 30 contain the Wake-up Register information. Local wake-up inputs L0:L3 can be used in both Normal and
Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 28).
Wake-up inputs can be configured by pair. L0 and L1 can be configured together, and L1 and L2, and L2 and L3 can be
configured together (Table 29).
Table 26. HSON Control Bits
Logic
HS State
0
HS OFF, in Normal and Standby modes.
1
HS ON, in Normal and Standby modes.(60)
Notes
60.
When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error
bits are latched in the IOR register.
Table 27. Input/Output Register Status Bits
Name
Logic
Description
V2LOW
0
V2LTH > 4.0V.
1
V2LTH < 4.0V.
HSOT
0
No HS over-temperature.
1
HS over-temperature.
VSUPLOW
0
VBF(EW) > 5.8V.
1
VBF(EW) < 5.8V.
DEBUG
0
SBC not in Debug mode.
1
SBC accepts command to go to Debug modes (no Watchdog).
Table 28. Wake-up Register
WUR
R/W
D3
D2
D1
D0
$100b
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
Reset Value
0
Reset Condition (Write)(61)
POR, NR2R, N2R, STB2R, STO2R
Notes
61.
See Table 13, page 46, for definitions of reset conditions.
Table 29. Wake-up Register Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0 L1:L1 L2 Config
L2 L3:L3 L4 Config
x
0
Inputs Disabled
x
0
1
High Level Sensitive
x
1
0
Low Level Sensitive
x
1
Both Level Sensitive
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