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參數(shù)資料
| 型號： | MDS212CG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 12-Port 10/100Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁數(shù)： | 22/111頁 |
| 文件大小： | 1609K |
| 代理商： | MDS212CG |
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MDS212
Data Sheet
22
Zarlink Semiconductor Inc.
3.0 The Media Access Control (MAC)
The MDS212 MAC contains twelve Fast Ethernet MACs, defined by the IEEE Standard 802.3 CSMA/CD. Each
Fast Ethernet MAC is connected to a Physical Layer (PHY) via the Reduced Media Independent Interface (RMII).
The MAC sublayer consists of a Transmit and Receive section and is responsible for data encapsulation/
decapsulation. Data encapsulation/decapsulation involves framing (frame alignment and frame synchronization),
handling source and destination addresses, and detecting physical medium transmission errors. The MAC also
manages half-duplex collisions, including collision avoidance and contention resolution (collision handling). The
MDS212 includes an optional MAC Control sublayer (“MAC Control”) used for IEEE Flow Control functions.
During frame transmission, the MAC transmit section encapsulates the data by prepending a preamble and a Start
of Frame Delimiter (SFD), inserts a destination and source address, and appends the Frame Check Sequence
(FCS) for error detection. In VLAN aware switches, the MAC inserts, replaces, or removes VLAN Tags from these
frame formats based on instructions from the Search Engine. When necessary, the MAC regenerates the Frame
Check Sequence and performs “padding” for frames of less than 64 bytes in size.
During frame reception, the MAC receive section verifies that the CRC is valid, de-serializes the data, and buffers
the frame into the Receive FIFO. The MAC then signals the Frame Engine, using Receive Direct Memory Access
(RxDMA), that data is available in the FIFO and is ready for storage.
3.1 MAC Configuration
MAC operations are configured through the Global Device Configuration Register (DCR2) and/or the MAC Control
and Configuration Registers (ECR0, ECR1), defined in the Register Definition Section of the MDS212 Datasheet.
The default settings for autonegotiation, flow control, frame length, and duplex mode may be changed and
configured by the user on a per-port basis, either in hardware or software.
3.2 The Inter-Frame Gap
The Inter-frame Gap (IFG), defined as 96 bit times, is the interval between successive Ethernet frames for the
MAC. Depending on traffic conditions, the measurement reference for the IFG changes. If a frame is successfully
transmitted without a collision, the IFG measurement starts from the deassertion of the Transmit Enable (TXEN)
signal. However, if a frame suffers a collision, the IFG measurement starts from the deassertion of the Carrier
Sense (CRS) signal.
3.3 Ethernet Frame Limits
A legal Ethernet frame size, defined by the IEEE specification, must be between 64 and 1518 bytes, referring to the
packet length on the wire. For transmitting or forwarding frames whose data lengths do not meet the minimum
requirements, the MAC appends extra bytes (padding) from the PAD field. Frames, longer than the maximum
length may either be forwarded or discarded, depending on the register configuration. Although the MAC may be
configured to forward oversized frames in the Device Configuration Register (DCR2), the frame buffers’ maximum
size of 1536 bytes cannot be exceeded. For VLAN Aware systems, the maximum frame size is increased from
1518 bytes to 1522 bytes to accommodate the 4-byte VLAN Tag.
3.4 Collission Handling and Avoidance
If multiple stations on the same network attempt to transmit at the same time, interference can occur causing a
collision. The MAC monitors the Carrier Sense (CRS) signal to determine if the medium is available before
attempting to transmit data. If the transmission medium is busy, the MAC defers (delays) its own transmissions to
decrease the load on the network. This is called collision avoidance.
If a collision occurs, the MAC ceases data transmission after the first 64 bytes of data and sends the jam sequence
to notify all connected nodes of a collision. This jam sequence will persist for 32 bit times. The jam sequence is a 32
bit predetermined pattern used to notify others of a collision on the network. If a collision occurs during preamble
generation, or within the first 64 bytes, the transmitter waits until the preamble is completed and then “backs off”
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