參數(shù)資料
型號(hào)： MDS212CG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： 12-Port 10/100Mbps Ethernet Switch
中文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝： 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁(yè)數(shù)： 46/111頁(yè)
文件大?。?/td> 1609K
代理商： MDS212CG
MDS212
Data Sheet
46
Zarlink Semiconductor Inc.
Figure 16 - Time Diagram of LED Interface
12.0 Data Forwarding Protocol and Data Flow
12.1 Data Forwarding Protocol
12.1.1 Frame Reception
For normal frame reception, a 128-byte block of frame data is stored in the RxFIFO. This block may be shorter if an
End of Frame (EOF) arrives. At that point, the RxDMA will request the use of the internal memory bus. When this
memory request is granted, the RxDMA will move the block from the RxFIFO to the Frame Data Buffer (FDB).
The service discipline is round robin for the 100/10Mbps ports. After the entire frame is moved to the frame data
buffer (FDB), a switch request will be sent to the Search Engine (Reference Search Engine Section)
12.1.2 Unicast Frame Forwarding
For forwarding of the unicast frame, the Search Engine first resolves the destination device and the destination
port, and sends a switch response back to the Frame Engine. The Frame Engine will obtain the type (unicast or
multicast), the destination port, and the destination device from the search response. After processing the search
response, the Frame Engine will notify the destination port that it has a frame to forward to the destination port’s
TxFIFO.
For local forwarding (e.g. the destination port is in the local device), the Frame Engine will send the job to the
Transmission Scheduling queue of the destination port.
For remote forwarding (i.e. the destination port is in the remote device), the Frame Engine will create a data
forwarding request command message (DATA_FWD_REQ), which is sent via the XPipe to the remote device. The
remote Frame Engine, after receiving this DATA_FWD_REQ message, will place a job in the Transmission
Scheduling queue of the destination port.
LED_CLKI/O
LED_SYNI/O
LED_DI/O
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
*1
Master dev sub-frame
16 slots
Slave dev sub-frame
16 slots
One Frame
256x80nsec
Cycle #0
Cycle #7
Cycle #8
Cycle #9
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
PO
P1
bit 0
bit 1
1* one pulse for every 256 cycles
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