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參數(shù)資料
| 型號： | MDS212CG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網絡接口 |
| 英文描述： | 12-Port 10/100Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁數(shù)： | 42/111頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MDS212CG |
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MDS212
Data Sheet
42
Zarlink Semiconductor Inc.
Note:
In unmanaged mode, the primary device may be the Master or the Slave. The master device is the bus
master (controls the bus), while the other device is a slave device.
10.1.5 Input/output Mapped Interface
The systems’ external CPU accesses the switch devices’ local memory using single-read/write or burst- read/write
I/O cycles. Burst I/O operations with auto address incrementing uses a 32-byte write data buffer and a 32-byte
cache read data buffer.
10.1.6 Interrupt Request
The CPU Interface accepts an Interrupt Request (IRQ) from each device connected to the interface, and supports
centralized interrupt arbitration and vector response. The interrupt output is an open-drain option with
programmable polarity.
10.2 Control Bus Cycle Waveforms
Figure 12 - Control Bus I/O and Flash Bus Access Operations
10.3 The CPU Interface in Unmanaged Mode
In unmanaged mode, the HISC processor of the Master device communicates with the slave device as a CPU
function. Three registers and one flag are used to communicate between the HISC processor and the CPU
Interface.
10.3.1 Arbiter
The arbiter of the XpressFlow MDS212 is an internal logic device used to determine which device will function as
the master device. The connections between the master device, slave device, and the CPU are used for debugging
purposes only (see Figure 13).
During Power On/Reset, the bootstrap pin, BS_PSD, determines which device will be the primary and activates the
arbiter of that device. At most, three devices, two MDS212 devices and one CPU, can operate on the CPU
Interface at the same time.
P_CLK
P_ADS#
P_RDY#
P_A[10:1]
P_BRDY#
P_BLAST#
one-wait state
wait Read Read
Read
Read
wait
wait
Read
Read cycle = 8 clks
Write cycle
Burst
Read cycle
Sample
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相關代理商/技術參數(shù) |
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| MDS217 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| MDS-21E09 | 制造商:ITT Interconnect Solutions 功能描述:BACKSHELL - Bulk |
| MDS21P-6AA-000 | 制造商:Amphenol Corporation 功能描述:MICRO D/18in WIRE 26AWG 7 STRD THRU HOLE |
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