MDS212
Data Sheet
92
Zarlink Semiconductor Inc.
Bit [9:0]
Bit [30:10]
Bit [31]
FCB_HANDLE
Reserved
H_RDY
FCB Handle Address
FCB Handle Ready
0=Not Ready 1=Ready
18.2.11.7 CPU Access Internal RAMs (Tables)
Usage:
(refer to section 9.0 “The High Density Instruction Set Computer (HISC)” on page 37 for details)
The CPU uses the following methods to access the five internal RAMs, including MCID, VLAN port mapping
(VMAP), BM control Table (BMCT), FCB and Transmission Queue control (QCNT).
Registers:
CPUIRCMD
:
Command register
CPUIRDAT0
:
Data Register for specific entry of content Bit[31:0]
CPUIRDAT1
:
Data Register for specific entry of content Bit[63:32]
CPUIRDAT2
:
Data Register for specific entry of content Bit[95 64]
CPUIRRDY
:
Data Read Ready.
CPU Reads FCB
CPU write the read command into CPUIRCMD with FCB Handle, W/R=0. And set C_RDY. Also, set
the table type = FCB, (CPUIRCMD[14]=1)
Frame Engine puts the specified FCB content into CPUIRDATL and CPUIRDATM
Frame Engine Clear C_RDY
Frame Engine set CPUIRRDY[0] to notify CPU that the FCB data is ready to be read.
CPU writes FCB
CPU writes the content of FCB into CPUIRDATL and CPUIRDATM
CPU writes the handle of FCB into CPUIRCMD [9:0], set CPUIRCMD [10] = 1,(write CMD),
set CPUIRCMD[31]=1, CMD_RDY and set the Table Index to FCB, (CPUIRCMD[14]=1).
Frame Engine clears CPUIRCMD [31], C_RDY, when Frame Engine reads FCB done
Apply the similar method to access the other four tables.
18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register
Access:
Address:
Command for CPU accesses five internal Tables
Non-Zero-Wait-State,Direct Access,Write/Read
h584
Bit [9:0]
Entry Index
Type = MCID(16)
Type = VMAP(256)
Type = BMCT(1K)
Type = FCB(1K)
Type = QCNT (64)
W/R
The index of specified entry
Entry index[3:0]
Entry index[7:0]
Entry index[9:0]
Entry index[9:0]
Entry index[5:0]
Write or Read the table entry
0=Read
1=Write
Bit [10]
31
30
10
9
0
H_RDY
FCB_Handle [11:0]
31
30
16
15
14
13
12
11
10
9
0
C_RDY
QCNT
FCB
BMCT
VMAP
MCID
W/R
Entry Index [9:0]