MDS213
Data Sheet
29
Zarlink Semiconductor Inc.
threshold, its associated output port is "blacklisted." Entering frames destined to this output port are discarded, until
the counter goes below the threshold. This threshold is programmed via registers BCT and BCHL. These counters
prevent complete depletion of buffers due to an overloaded port, thus allow frames destined for non-congested
ports to enter the system. This effectively avoids head-of-line blocking.
The Frame Engine also keeps a buffer counter for multicast traffic types. The buffers occupied by incoming
multicast frames are limited. This prevents multicast frames from blocking unicast ones from entering the system.
The threshold for multicast traffic types is programmed via register MBCR.
5.0 Frame Buffer Memory
5.1 Frame Buffer Memory configuration
The MDS213 system utilizes external SRAM for its Frame Buffer Memory configuration, where the size of memory
supported is MB, 1MB and 2MB configurations. The following table shows four memory configuration examples
for the MDS213 system.
The following figure shows the connections between the Frame Buffer Memory and the MDS213 for one-bank and
two-bank memory configurations.
Figure 4 - Frame Buffer Memory Configuration
SRAM Type
One Bank
Two Bank
Address
Size
Address
Size
64Kx32
L_A[18:3]
MB
L_A[19:3]
1M
128Kx32
L_A[19:3]
1MB
L_A[20:3]
2M
Table 1 - Type and Size of Memory Chips
SRAM
64Kx32
SRAM
64Kx32
L
SRAM
64Kx32
SRAM
64Kx32
MDS213
L_D[31:0]
L_D[63:32]
L
One Bank 0.5M
64Kx32
L_A[18:3]
SRAM
64Kx32
SRAM
64Kx32
MDS213
L_D[31:0]
L_D[63:32]
L
One Bank 1.5M
128Kx32
L_A[19:3]
MDS213
SRAM
128Kx32
SRAM
128Kx32
L
CE
L_D[31:0]
L_D[31:0]
L_A[18:3]
L_A[19]
L_D[63:32]
CE
L_D[63:32]
Two Bank 1M
64Kx32
SRAM
SRAM
64Kx32
L
SRAM
128K64Kx32
SRAM
128Kx32
L
MDS213
CE
L_D[31:0]
L_D[31:0]
L_A[19:3]
L_A[20]
L_D[63:32]
CE
L_D[63:32]
Two Bank 1M
128Kx32