MDS213
Data Sheet
77
Zarlink Semiconductor Inc.
18.2.3.6 MBCR - Multicast Buffer Control Register
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
Address:
h79C
Bit [4:0]
MAX_MC_FD
Maximum Number of Multicast Frames allowed for forwarding
Bit [10:5]
RMC_BUF_RSV
Number of buffers reserved for receiving remote Multicast Frames
Bit [19:11]
MAX_CNT_LMT
Maximum Number of Multicast Frames allowed per device
Bit [21:20] MCFTH
Multicast Forwarding Threshold: Watermark for forwarding FF to drop
regular multicast packet if IPMC bit in DCR2[26] is ON. CPU can set four
level watermarks, which are programmable
00= 25%
01=50%
10= 75%
11= 100%
Bit [31:22] Reserved
18.2.3.7 AMA - RAM Counter Block Access Register
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
Address:
h7A0
RAM counter block contains 13 counter blocks (one for each port) Port 0 counter block starts at address 0.) The
size of each block is 16 double words, which consist of total 30 statistic counters. has total The size and type of
each counter is referred to the register ECR4.
CPU uses this register to access the specified statistic counter by setting the start address of RAM counter block
and the length.
Bit [3:0]
BST_CNT
Read/write burst (length) of RAM Block. (Unit = 1double words)
Bit [10:4]
ST_ADR
Read/Write Start Address.
Bit [14:11]
Reserved
Bit [15]
W/R
RAM Block Access Write/Read indicator
1 = Write
0 = Read
Bit [31:16] Reserved
Note:
The access range is equal to from ST_ADR to END_ADR= S_ADR+ BST_CNT. The END_ADR cannot cross
the boundary of each port block, i.e., 8 double words.
31
0
11 10
MCTH
22 21 20 19
5 4
RMC_BUF_RSV
MAX_CNT_LMT
MAX_MC_FD
31
0
11 10
W/
R
16 15 14
BST_CNT
ST_ADR
4 3