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參數(shù)資料
| 型號(hào)： | MDS213 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | 12口10/100Mbps千兆以太網(wǎng)交換機(jī) |
| 文件頁(yè)數(shù)： | 39/120頁(yè) |
| 文件大小： | 1678K |
| 代理商： | MDS213 |
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MDS213
Data Sheet
39
Zarlink Semiconductor Inc.
The XPipe interface employs 32 data signals and three control signals for each direction. The pin connections
between two MDS213 devices are depicted in Figure 8. These 32 data signals form a 32-bit-wide transmission data
pipe that carries XpressFlow messages to and from the devices. The direction of all signals are from the source to
the target device, except for the flow control signal, which sends messages in the opposite direction; from the target
to the source. The three control signals consist of: a Transmit Clock signal, a Transmit Data Enable signal, and a
Flow Control signal.
The Transmit Clock signal (X_DCLKO), provides a synchronous clock to sample the data signals at the target
device. The source device provides the Transmit Data Enable signal (X_DENO) that envelops an entire XPipe
message (including the Header and the Payload) and is used to identify the message boundary from the received
data stream. The timing relationship between the data, clock, and data enable signals are described in the XPipe
Timing (Section 10.2).
The Flow Control signal (X_FC) monitors the state of the receiving queue at the target end to prevent XPipe
message loss. When the target end does not have enough space to accommodate an entire XPipe message, the
target device sends a XOFF signal by driving the X_FCO signal to LOW. The source device will stop further
transmission until the X_FCI signal asserts the XON state, which is an active HIGH (Refer to Table 4).
Table 4 - Summary Description of the Source and Target End Signals
The XPipe Message Header provides the payload size, type of message, routing information, and control
information for the XPipe incoming message. The routing information includes the device ID and port ID. The
header size is dependent upon the message types and may be 2 to 4 words in length.
Figure 9 - XPipe Message Header
8.2 XPipe Timing
The source device generates the X_CLKO signal to provide a synchronous transmit data clock. The Receiver will
then sample the data on the falling (negative) edge of the clock, as shown in Figure 10.
To identify the boundary between the XPipe messages and the data stream, the source device uses the X_DENO
signal to envelop the entire XPipe message. That is, a rising (positive) edge at the beginning of the first double word
Signal Name
Description
Source End
Target End
X_DO[31:0]
X_DI[31:0]
32-bit-wide Transmit Data Bus - Includes a XPipe Message
Header and follows by the data payload
X_DCLKO
X_DCLKI
Transmit Clock - Synchronous data clock provided by the source
end
X_DENO
X_DENI
Transmit Data Enable - Provided by the source end to envelop
the entire XPipe message
X_FCI
X_FCO
Flow Control Signal- A flow control pin from the target end to
signal the source end to active XON/XOFF.
Data Payload
2-4 Words Header
XpipeFlow Message
Header
0-64 Words Payload
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相關(guān)代理商/技術(shù)參數(shù) |
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| MDS213CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:12-Port 10/100Mbps + 1Gbps Ethernet Switch |
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| MDS21P-6AA-000 | 制造商:Amphenol Corporation 功能描述:MICRO D/18in WIRE 26AWG 7 STRD THRU HOLE |
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