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| 型號： | MFRC52201HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 28/92頁 |
| 文件大?。?/td> | 691K |
| 代理商： | MFRC52201HN1 |
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MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
28 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit
can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
The MFRC522 can generate an interrupt signal when:
ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation 3
:
(3)
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4
:
(4)
8.4 Interrupt request system
The MFRC522 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
8.4.1
Interrupt sources overview
Table 18
shows the available interrupt bits, the corresponding source and the condition for
its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by
the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see
Table 149 on
page 67
).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
HiAlert
64
FIFOLength
–
(
)
WaterLevel
≤
=
LoAlert
FIFOLength
WaterLevel
≤
=
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| MFRC52201HN1,115 | 功能描述:RFID應(yīng)答器 RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52201HN1,118 | 功能描述:RFID應(yīng)答器 RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52201HN1,151 | 功能描述:RFID應(yīng)答器 Contactless Reader 32-Pin RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52201HN1,157 | 功能描述:RFID應(yīng)答器 CL READER IC’S RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52201HN1/TRAYB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
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