參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 52/92頁
文件大?。?/td> 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
52 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
9.3.2.11
Reserved register 1Ah
Functionality is reserved for future use.
Table 73.
Bit
Symbol
Access
Table 74.
Bit
7 to 0
9.3.2.12
Reserved register 1Bh
Functionality is reserved for future use.
Table 75.
Bit
Symbol
Access
Table 76.
Bit
7 to 0
9.3.2.13
MfTxReg register
Controls some MIFARE communication transmit parameters.
Table 77.
Bit
Symbol
Access
4
TPrescalEven
R/W
If set to logic 0 the following formula is used to calculate the timer
frequency of the prescaler:
f
timer
= 13.56 MHz / (2*TPreScaler+1).
If set to logic 1 the following formula is used to calculate the timer
frequency of the prescaler:
f
timer
= 13.56 MHz / (2*TPreScaler+2).
(Default TPrescalEven bit is logic 0)
changes the time-constant of the internal PLL during data
reception
Remark:
if set to 00b the PLL is frozen during data reception
changes the time-constant of the internal PLL during burst
3 to 2 TauRcv[1:0]
-
1 to 0 TauSync[1:0]
-
Table 72.
Bit
DemodReg register bit descriptions
…continued
Symbol
Value Description
Reserved register (address 1Ah); reset value: 00h bit allocation
7
6
5
4
3
2
1
0
reserved
-
Reserved register bit descriptions
Symbol
reserved
Description
reserved for future use
Reserved register (address 1Bh); reset value: 00h bit allocation
7
6
5
4
3
2
1
0
reserved
-
Reserved register bit descriptions
Symbol
Description
reserved
reserved for future use
MfTxReg register (address 1Ch); reset value: 62h bit allocation
7
6
5
reserved
-
4
3
2
1
TxWait[1:0]
R/W
0
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