參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網絡
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 8/92頁
文件大?。?/td> 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
8 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the MfRxReg register’s ParityDisable bit.
8.1 Digital interfaces
8.1.1
Automatic microcontroller interface detection
The MFRC522 supports direct interfacing of hosts using SPI, I
2
C-bus or serial UART
interfaces. The MFRC522 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The MFRC522 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections.
Table 5
shows the different connection
configurations.
Table 5.
Pin
Fig 6.
Data coding and framing according to ISO/IEC 14443 A
001aak585
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
parity
odd
parity
odd
parity
start bit is 1
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
8-bit data
8-bit data
8-bit data
odd
parity
odd
parity
even
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the frame
Connection protocol for detecting different interface types
Interface type
UART (input)
RX
0
0
TX
MX
DTRQ
-
-
-
-
SPI (output)
NSS
0
1
MISO
MOSI
SCK
-
-
-
-
I
2
C-bus (I/O)
SDA
1
EA
SCL
ADR_0
ADR_1
ADR_2
ADR_3
ADR_4
ADR_5
SDA
I2C
EA
D7
D6
D5
D4
D3
D2
D1
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