參數(shù)資料
型號： MJ80C32U-25:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁數(shù)： 22/109頁
文件大小： 10824K
25
AT32UC3A
9.3
Programming Model
9.3.1
Register file configuration
The AVR32UC register file is shown below.
Figure 9-3.
The AVR32UC Register File
9.3.2
Status register configuration
The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 9-4 on
page 25 and Figure 9-5 on page 26. The lower word contains the C, Z, N, V and Q condition
code flags and the R, T and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 9-4.
The Status Register High Halfword
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
SP_APP
SP_SYS
R12
R11
R9
R10
R8
Exception
NMI
INT1
INT2
INT3
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SM PC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 31
0
Bit 16
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 3 Mask
Interrupt Level 2 Mask
1
0
1
0
FE
I0M
GM
M1
-
D
M0
EM
I2M
DM
-
M2
LC
1
-
Initial value
Bit name
I1M
Mode Bit 0
Mode Bit 1
-
Mode Bit 2
Reserved
Debug State
-
I3M
Reserved
Exception Mask
Global Interrupt Mask
Debug State Mask
32058K
AVR32-01/12
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