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參數(shù)資料
| 型號： | MJ80C32U-25:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 37/109頁 |
| 文件大小： | 10824K |
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281
7593L–AVR–09/12
AT90USB64/128
2 - CTRLDIR - Control Direction (flag, and bit for debug purpose)
Set by hardware after a SETUP packet, and gives the direction of the following packet:
- 1 for IN endpoint
- 0 for OUT endpoint
Can not be set or cleared by software.
1-0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) flag
Set by hardware to indicate the number of the current bank:
00b
Bank0
01b
Bank1
1xb
Reserved
Can not be set or cleared by software.
7 - FIFOCON - FIFO Control bit
For OUT and SETUP Endpoint:
Set by hardware when a new OUT message is stored in the current bank, at the same time than
RXOUT or RXSTP.
Clear to free the current bank and to switch to the following bank. Setting by software has no
effect.
For IN Endpoint:
Set by hardware when the current bank is free, at the same time than TXIN.
Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
6 - NAKINI - NAK IN Received Interrupt flag
Set by hardware when a NAK handshake has been sent in response of a IN request from the
host. This triggers an USB interrupt if NAKINE is sent.
Shall be cleared by software. Setting by software has no effect.
5 - RWAL - Read/Write Allowed flag
Set by hardware to signal:
- for an IN endpoint: the current bank is not full, that is, the firmware can push data into the FIFO,
- for an OUT endpoint: the current bank is not empty, that is, the firmware can read data from the
FIFO.
The bit is never set if STALLRQ is set, or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for the control endpoint.
Bit
7
6
5
43210
FIFOCON
NAKINI
RWAL
NAKOUTI
RXSTPI
RXOUTI
STALLEDI
TXINI
UEINTX
Read/write
R/W
Initial value
00
0
00000
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