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參數(shù)資料
| 型號： | MJ80C32U-25:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 94/109頁 |
| 文件大?。?/td> | 10824K |
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70
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit setting. Table
11-2 shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 11-2.
Compare Output Mode, non-PWM Mode
Table 11-3 shows COM0A[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode.
Table 11-3.
Compare Output Mode, Fast PWM Mode
Note:
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is
ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 65 for more details.
Table 11-4 shows COM0A[1:0] bit functionality when WGM0[2:0] bits are set to phase correct PWM mode.
Table 11-4.
Compare Output Mode, Phase Correct PWM Mode
Note:
When OCR0A equals TOP and COM0A1 is set, the Compare Match is ignored, but the set or clear is done at
TOP. See “Phase Correct PWM Mode” on page 66 for more details.
Bits 5:4 – COM0B[1:0] : Compare Match Output B Mode
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
Set OC0A on Compare Match
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
Set OC0A at BOTTOM (non-inverting mode)
1
Set OC0A on Compare Match
Clear OC0A at BOTTOM (inverting mode)
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match
when down-counting.
1
Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match
when down-counting.
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