- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25623 > MJ80C32U-25:D (ATMEL CORP) MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號： | MJ80C32U-25:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 50/109頁 |
| 文件大?。?/td> | 10824K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁
30
AT32UC3A
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
9.4.2
Exceptions and interrupt requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus
Error) can not be masked. When an event is accepted, hardware automatically sets the
mask bits corresponding to all sources with equal or lower priority. This inhibits accep-
tance of other events of the same or lower priority, except for the critical events listed
above. Software may choose to clear some or all of these bits after saving the neces-
sary state if other priority schemes are desired. It is the event source’s responsability to
ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2 or INT3, regis-
ters R8-R12 and LR are also automatically stored to stack. Storing the Status Register
ensures that the core is returned to the previous execution mode when the current
event handling is completed. When exceptions occur, both the EM and GM bits are set,
and the application may manually enable nested exceptions if desired by clearing the
appropriate bit. Each exception handler has a dedicated handler address, and this
address uniquely identifies the exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown inTable 9-4, is
loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2 or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
9.4.3
Supervisor calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
9.4.4
Debug requests
The AVR32 architecture defines a dedicated debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
32058K
AVR32-01/12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C32E-36:RD | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
| S80C32-40:R | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 |
| S80C52EXXX-30:D | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
| SC80C52XXX-36/883 | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| S83C154TXXX-25 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MJ8100 | 制造商:ASI 功能描述:8100 N11E4C |
| MJ8100R | 制造商:SEME-LAB 制造商全稱:Seme LAB 功能描述:Bipolar PNP Device in a Hermetically sealed TO39 |
| MJ-82-1 | 制造商:SPC Multicomp 功能描述:SOCKET PCB DC POWER 制造商:SPC Multicomp 功能描述:SOCKET, PCB, DC POWER 制造商:SPC Multicomp 功能描述:SOCKET, PCB, DC POWER; Gender:Receptacle; Connector Mounting:PCB; Contact Termination:Through Hole Vertical; Connector Mounting Orientation:PCB; Connector Type:Standard Power Entry ;RoHS Compliant: Yes |
| MJ8250FE | 制造商:Ohmite Mfg Co 功能描述: |
| MJ8251F | 制造商:Ohmite Mfg Co 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。