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參數(shù)資料
| 型號(hào)： | MJ80C32U-25:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁(yè)數(shù)： | 64/109頁(yè) |
| 文件大?。?/td> | 10824K |
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43
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 10-2. General Digital I/O(1)
Note:
1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP
are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description” on
page 56, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, the PUExn
bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an
output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is
written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
WEx
SYNCHRONIZER
WDx:
WRITE DDRx
WRx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
clk
I/O:
I/O CLOCK
RDx:
READ DDRx
WEx:
WRITE PUEx
REx:
READ PUEx
D
L
Q
REx
RESET
Q
D
Q
QD
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
D
A
TA
BUS
SLEEP
SLEEP:
SLEEP CONTROL
Pxn
I/O
WPx
RESET
Q
QD
CLR
PUExn
0
1
WRx
WPx:
WRITE PINx REGISTER
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