參數(shù)資料
型號(hào)： MK10X512VMD100
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PBGA144
封裝： 13 X 13 MM, MAPBGA-144
文件頁數(shù)： 41/66頁
文件大?。?/td> 984K
代理商： MK10X512VMD100
Table 28. 12-bit DAC operating requirements (continued)
Symbol
Desciption
Min.
Max.
Unit
Notes
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
n
Resolution
12
—
12
b
IDDA_DACLP Supply current — low-power mode
—
150
μA
IDDA_DACH
P
Supply current — high-speed mode
—
700
μA
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
100
200
μs
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
—
15
30
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
5
μs
tCCDACHP Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
1
TBD
—
μs
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
0
100
—
mV
Vdacouth
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
100
—
VDACR
mV
INL
Integral non-linearity error — high speed mode
±3
—
±8
LSB
DNL
Differential non-linearity error — VDACR > 2 V
±0.5
—
±1
LSB
DNL
Differential non-linearity error — VDACR = VRE‐
FO (1.15 V)
±0.5
—
±1
LSB
VOFFSET
Offset error
±0.4
—
±0.8
%FSR
EG
Gain error
±0.1
—
±0.6
%FSR
PSRR
Power supply rejection ratio, VDDA > = 2.4 V
60
90
dB
TCO
Temperature coefficient offset voltage
—
TBD
—
μV/C
TGE
Temperature coefficient gain error
—
TBD
—
ppm of
FSR/C
AC
Offset aging coefficient
—
TBD
μV/yr
Rop
Output resistance load = 3 kΩ
—
250
Ω
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
46
Preliminary
Freescale Semiconductor, Inc.
Preliminary
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