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參數(shù)資料
| 型號(hào)： | MK40X512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁(yè)數(shù)： | 38/68頁(yè) |
| 文件大?。?/td> | 1005K |
| 代理商： | MK40X512VMD100R |
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4. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA
Supply current
TBD
590
TBD
μA
ILKG
Leakage current
PGA disabled
—
< 1
TBD
μA
G
Gain2
PGAG=0
PGAG=1
PGAG=2
PGAG=3
PGAG=4
PGAG=5
PGAG=6
TBD
1
2
3.9
TBD
29.9
TBD
dB
RAS < 100Ω
GA
Gain error
—
±0.5
dB
RAS < 100Ω
BW
Input signal band‐
width
16-bit modes
< 16-bit modes
—
4
40
kHz
PSRR
Power supply re‐
jection ration
Gain=1
TBD
—
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
CMRR
Common mode
rejection ratio
Gain=1
Gain=64
TBD
—
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
VOFS
Input offset volt‐
age
—
0.2
TBD
mV
Gain=1, ADC
Averaging=32
TGSW
Gain switching
settling time
—
TBD
10
s
dG/dT
Gain drift over
temperature
Gain=1
Gain=64
—
TBD
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
—
TBD
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
Gain=1
Gain=64
—
TBD
%/V
VDDA from 1.71
to 3.6V
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
43
Preliminary
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