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參數(shù)資料
| 型號： | MK40X512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 39/68頁 |
| 文件大小： | 1005K |
| 代理商： | MK40X512VMD100R |
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Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
EIL
Input leakage er‐
ror
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current op‐
erating ratings)
VPP,DIFF
Maximum differ‐
ential input signal
swing
[(VREFPGA × 2.33) - 0.2] / (2 ×
Gain)
V
SNR
Signal-to-noise
ratio
Gain=1
Gain=64
TBD
8.3
57.7
—
dB
Average=32
THD
Total harmonic
distortion
Gain=1
Gain=64
TBD
87.3
85.3
—
dB
Average=32,
fin=100Hz
SFDR
Spurious free dy‐
namic range
Gain=1
Gain=64
TBD
92.42
92.54
—
dB
Average=32,
fin=100Hz
ENOB
Effective number
of bits
Gain=1, Average=4
Gain=1, Average=8
Gain=64, Average=4
Gain=64, Average=8
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32
TBD
12.3
12.7
8.4
8.7
13.4
13.1
12.6
11.8
11.1
10.2
9.3
—
bits
SINAD
Signal-to-noise
plus distortion ra‐
tio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Gain = 2PGAGx
3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
44
Preliminary
Freescale Semiconductor, Inc.
Preliminary
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