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參數(shù)資料
| 型號(hào)： | ML6510 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Series Programmable Adaptive Clock Manager(系列可編程自適應(yīng)時(shí)鐘管理器) |
| 中文描述： | 系列可編程自適應(yīng)時(shí)鐘管理器（系列可編程自適應(yīng)時(shí)鐘管理器） |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510 |
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ML6510
10
REV. 1.0 10/25/2000
Adaptive Deskew buffers
Each copy of the clock is driven by an adaptive deskew
buffer. The deskew buffer compensates for skew time
automatically in accordance to the flight time delay it
senses from the reflection on the transmission line.
Figure 4 shows the simplified functional block diagram of
the deskew circuit. The phase of the sense signal and the
driver signal is presented to a three-input phase
comparator and compared with the reference signal. The
phase comparator then controls the voltage controlled
delay in the output drive line to match the delay of the
fixed reference delay line. Therefore, the sum of the delay
of the driver circuit, PCB trace delay, rise time delay at
the load and the adjustable delay will always equal the
fixed maximum delay.
The sense circuit has an internal level detect such that
any skew caused by loading is also accounted for. Since
the delay of the circuit is matched for the entire loop, the
phase of all the drivers are in close alignment at the
inputs of the load.
CLOCK IN
FIXED
MAX
DELAY
PHASE
DETECTOR
SENSE
DRIVE
VOLTAGE
CONTROLLED
DELAY
LOAD
Figure 4. Deskew Circuit Block Diagram.
Load Conditions
The ML6510 has been designed to drive the wide range of
load conditions that are encountered in a high frequency
system. The eight output clock loads can each vary within a
range of trace length and lumped capacitive load, and the
ML6510 will maintain the low skew characteristics
specified in Electrical Characteristics. The clock skew can
be further minimized by providing some first-order
matching between any two loads that require particularly
well-matched clocks.
The ML6510-80 produces a 5V swing at the load and
requires a single external termination resistor for each
output. The ML6510-130 produces a 3V swing at the load
and requires two external termination resistors for each
output. The FB input pin is connected to the other side of
the termination resistor R1 or R2, with a short connection.
Termination resistor valves should be chosen as follows:
R
Z
R
Z
R
Z
1
2
1 5
.
3
3
0
0
0
=
=
×
=
×
Trace
RESISTOR
Values
R2
Impedance
Z0
R1
R3
40y
50y
63y
40
50
63
60
75
95
120
150
189
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6510CQ-130 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6510CQ80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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