參數(shù)資料
型號(hào): ML6510
廠商: Fairchild Semiconductor Corporation
英文描述: Series Programmable Adaptive Clock Manager(系列可編程自適應(yīng)時(shí)鐘管理器)
中文描述: 系列可編程自適應(yīng)時(shí)鐘管理器(系列可編程自適應(yīng)時(shí)鐘管理器)
文件頁數(shù): 6/18頁
文件大?。?/td> 150K
代理商: ML6510
ML6510
6
REV. 1.0 10/25/2000
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Programming Timing Characteristics
(continued)
t
M1
MAIN mode MCLK high time
900
ns
t
M2
MAIN mode MCLK low time
900
ns
t
M3
MAIN mode MCLK period
1800
ns
t
M4
MAIN mode
MCLK to MD
OUT
valid
(EEPROM read time)
900
ns
Note 1:
Note 2:
Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
If ML6510-130 is used in a master-slave mode, the maximum operating frequency is 120MHz.
ML6510 configured with bit CM = 0:
TTL INPUT CLOCK
LOAD [0-7]
1st Order Match
LOAD [0-7] with
no 1st order match
tSKEWF
tSKEWB
tSKEWR
tSKEWIO
PECL INPUT CLOCKS
OR
OR
CLK
INH
CLK
INL
V
ICM
AVCC – 0.4V
2.0 V
Note:
All skew is measured at the device load input pin, NOT at the ML6510 clock output pin. Skew is always a positive number, regardless of which edge is leading and
which is trailing.
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