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參數(shù)資料
| 型號： | ML6510 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Series Programmable Adaptive Clock Manager(系列可編程自適應(yīng)時鐘管理器) |
| 中文描述： | 系列可編程自適應(yīng)時鐘管理器（系列可編程自適應(yīng)時鐘管理器） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510 |
ML6510
REV. 1.0 10/25/2000
11
PCB trace impedance
Z
0
= 40
to 65
Lumped
CL
≤
20pF
FBX
CLKX
ML6510-130
FIRST-ORDER
MATCHED LOADS
ML6510-130
GENERIC
LOAD
R2
One way trip delay < t
RANGE
/2
PCB trace impedance
Z
0
= 40
to 65
Lumped
CLX
≤
20pF
FBX
CLKX
LOAD
LOAD
R2
R3
Length L
X
PCB trace impedance
Z
0
= 40
to 65
Lumped
CLY
≤
20pF
FBY
CLKY
LOAD
R2
R3
One way trip delay < t
RANGE
/2
Length L
Y
|C
LX
– C
LY
| < 5pF
|L
X
– L
Y
| < 4"
Z
OX
= Z
OY
R3
PCB trace impedance
Z
0
= 40
to 65
Lumped
CL
≤
20pF
FBX
CLKX
ML6510-80
FIRST-ORDER
MATCHED LOADS
ML6510-80
GENERIC
LOAD
R1
One way trip delay < t
RANGE
/2
PCB trace impedance
Z
0
= 40
to 65
Lumped
CLX
≤
20pF
FBX
CLKX
LOAD
LOAD
R1
Length L
X
PCB trace impedance
Z
0
= 40
to 65
Lumped
CLY
≤
20pF
FBY
CLKY
LOAD
R1
One way trip delay < t
RANGE
/2
Length L
Y
|C
LX
– C
LY
| < 5pF
|L
X
– L
Y
| < 4"
Z
OX
= Z
OY
external Input clocks
The external input clock to the ML6510 can be either a
differential Pseudo-ECL clock or a single-ended TTL
clock. This is selected using the CS bit in the serial shift
register. For the single-ended TTL clock tie the CLK
INH
and CLK
INL
pins together. The ML6510 ensures that there
is a well-defined phase difference between the input and
output clocks.
RESET
and lock
When
RESET
is de-asserted, the internal programming
logic will become active, loading in the configuration
bits (see Programming the ML6510). Once the
configuration is loaded, the PLL will lock onto the
reference signal, and then the deskew blocks will adapt
to the load conditions. When all eight output clocks are
stable and deskewed, LOCK will be asserted. The asserted
polarity of lock is high. Thus, LOCK can be used to
indicate that the system is ready, or it can be used to
drive the
RESET
input of another PACMan in a clock
tree.
CHIP
VCC
RESET
LOCK
tRESET
tLOCK
tLOCK
PROGRAM IN THE
CONFIGURATION
PROGRAM IN THE
CONFIGURATION
0
5V
RESET
may be reasserted at any time to reset the chip
operations. Following a
RESET
assertion of valid pulse
width (see Programming Electrical Characteristics), the
ML6510 must again be loaded with a configuration, then
it will re-lock and reassert lock when all eight clock
outputs are stable and deskewed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6510CQ-130 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6510CQ80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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