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參數(shù)資料
| 型號(hào)： | ML6510 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Series Programmable Adaptive Clock Manager(系列可編程自適應(yīng)時(shí)鐘管理器) |
| 中文描述： | 系列可編程自適應(yīng)時(shí)鐘管理器（系列可編程自適應(yīng)時(shí)鐘管理器） |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510 |
ML6510
REV. 1.0 10/25/2000
9
PHASE
DETECTOR
÷
(M + 1)
[
÷
1 TO 64]
LOOP
FILTER
VCO
80-160 MHz
÷
2
R
MAXIMUM
DELAY
1
0
CM BIT
÷
(N + 1)
[
÷
1 TO
÷
128]
CLK
INH
CLK
INL
CS BIT
TTL TO ECL
1
0
SYS_CLK
TO DESKEW BUFFERS
ECL INPUT BUFFER
1
0
TEST
RCLKH
RCLKL
Example:
Generating a 2x clock input frequency = 33 MHz
Set R = 01 (output range 40 – 80 MHz), N = 5 (0000101),
M = 2 (000010), M/S = 0
f
f
N
(
M
(
MHz
33
MHz
VCO
REF
R
=
×
+
)
×
+
)
=
×
×
3
=
1
2
1
6
2
132
1
f
OUT
= f
VCO
/2
R
= 132 MHz/2
1
= 66 MHz
Example:
Generating a 1x clock Input frequency = 66 MHz
Set R = 01 (output range 40–80 MHz), set M = 0
(000000), N = 0 (0000000), M/S = 0
f
MHz
66
MHz
VCO
=
×
=
1 2
1
132
1
f
OUT
= f
VCO
/2
R
= 132 MHz/2
1
= 66 MHz
For doing frequency multiplication and division, keep
M 2 and N 2 for the lowest skew between input
clock and output clock.
Several configurations for doing
frequency multiplication and division are included in the
8 configurations stored in the on-chip ROM (see
PROGRAMMING the ML6510).
Figure 3. ML6510 Clock Generation Block Diagram.
input clock and output clocks. It can thus generate a 2x
or 4x or 0.5x frequency multiplication or division from
input to output (e.g. 33 MHz input, 66 MHz output or 66
MHz input, 33 MHz output, etc.). It also can generate a
1x frequency output. The VCO frequency is defined by:
f
f
N
(
M
(
VCO
REF
R
=
×
+
)
×
+
)
1
2
1
and the output frequency is still given by:
f
OUT
= f
VCO
/2
R
R1
R0
INPUT/OUTPUT RANGE
0
0
80-130 MHz
0
1
40–80 MHz
1
0
20–40 MHz
1
1
10–20 MHz
Note: R implies R1, R0; for -80 version, Not valid: Defaults to R = 01
The VCO still must remain in the range 80–160 MHz, and
the minimum phase detector input frequency is 625kHz =
(80 MHz/128). Thus the product of (N + 1) and 2
R
should
be limited to 128:
(N + 1) x 2
R
- 128
to make sure that the
phase detector inputs
remain above the minimum
frequency.
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