參數(shù)資料
型號(hào): ML6510
廠商: Fairchild Semiconductor Corporation
英文描述: Series Programmable Adaptive Clock Manager(系列可編程自適應(yīng)時(shí)鐘管理器)
中文描述: 系列可編程自適應(yīng)時(shí)鐘管理器(系列可編程自適應(yīng)時(shí)鐘管理器)
文件頁(yè)數(shù): 14/18頁(yè)
文件大小: 150K
代理商: ML6510
ML6510
14
REV. 1.0 10/25/2000
Register Definitions
REGISTER
SIZE
FUNCTION
N
7 bit
This register is used to define the ratio for the desired frequency of the primary clock.
R
2 bit
This register defines the frequency of the primary clocks, CLK [0-7].
CM
1 bit
Set CM = 1 when the PECL input reference clock is from another 6510 reference clock output. Set
CM = 0 if the clock reference is TTL or PECL from an external source and minimum phase error
between input and output is desired.
CS
1 bit
CS = 0 selects TTL input clock, CS = 1 selects PECL input clock.
TEST
1 bit
When set to 1, the PLL is bypassed for low frequency testing.
M
6 bit
This register is used to define the ratio for the desired frequency of the primary clock.
DDSK
1 bit
When DDSK is set to 1, deskew is disabled. The chip will provide low skew clocks at the chip output
pins, but trace length variations will not be compensated. When DDSK is set to 0, normal deskew will
provide low skew clocks at the loads. This bit is only for ML6510-130.
ML6510-80 Shift register chain
PC B trace impedance
0
= 50
Lumped
CL
20pF
FBX
C LKX
ML6510-80
FIRST-O RD ER
MATC H ED LOAD S
ML6510-80
G ENERIC
LOAD
R1
O ne way trip delay < t
RANG E
/2
PC B trace impedance
0
= 50
Lumped
20pF
FBX
C LKX
LOAD
LOAD
R1
Length L
X
PC B trace impedance
Z
0
= 50
Lumped
CLY
20pF
FBY
C LKY
LOAD
Z
O X
= Z
OY
R1
O ne way trip delay < t
RANG E
/2
Length L
Y
|C
LX
– C
LY
| < 5pF
|L
X
– L
Y
| < 4"
ML6510-130 Shift register chain
N1
N2
N3
N4
N5
N6
MSB
R0
LSB
R1
MSB
CS
M0
LSB
TEST
M1
M2
M3
M4
M5
MSB
N0
LSB
SERIAL DATA IN
(from EEPROM,
or
μ
Processor,
or internal ROM)
CM
DDSK
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