
MOTOROLA
Chapter 3. Device Programming
3-29
3.2.5 Error Handling Registers
Chapter 9, “Error Handling,” describes specific error conditions and how the MPC106
responds to them. The registers at offsets 0xB8, 0xB9, and 0xC0 through 0xCB control the
error handling and reporting for the MPC106. The following sections provide descriptions
of these registers.
3.2.5.1 ECC Single-Bit Error Registers
The ECC single-bit error registers are two 8-bit registers used to control the reporting of
ECC single-bit errors. See Chapter 9, “Error Handling,” for more information. The ECC
single-bit error counter, shown in Figure 3-12, maintains a count of the number of single-bit
errors that have been detected. Table 3-16 describes the bits of the ECC single-bit error
counter.
Figure 3-12. ECC Single-Bit Error Counter Register—0xB8
The ECC single-bit error trigger, shown in Figure 3-13, provides a threshold value, that,
when equal to the single-bit error count, triggers the MPC106 error reporting logic.
Table 3-17 describes the bits of the ECC single-bit error trigger.
Figure 3-13. ECC Single-Bit Error Trigger Register—0xB9
Table 3-16. Bit Settings for ECC Single-Bit Error Counter Register—0xB8
Bit
Name
Reset
Value
Description
7–0
ECC single-bit error
counter
All 0s
These bits maintain a count of the number of ECC single-bit errors
that have been detected and corrected. If this value equals the value
contained in the ECC single-bit error trigger register, then an error
will be reported (provided ErrEnR1[2] = 1).
Table 3-17. Bit Settings for ECC Single-Bit Error Trigger Register—0xB9
Bit
Name
Reset
Value
Description
7–0
ECC single-bit error
trigger
All 0s
These bits provide the threshold value for the number of ECC
single-bit errors that are detected before reporting an error condition.
7
0
ECC Single-Bit Error Counter
7
0
ECC Single-Bit Error Trigger