
MOTOROLA
Chapter 3. Device Programming
3-11
3.1.3 Emulation Mode Address Map
The emulation mode address map is actually a subset of address map B that has a
programmable boundary, as seen by the PCI bus, between the system memory space and
the PCI memory space. The emulation mode address map is fully compliant with the PC
emulation option described in the CHRP specification.
When configured for the emulation mode address map, the MPC106 translates addresses
across the 60x and PCI buses as shown in Figure 3-6. Table 3-7, Table 3-8, and Table 3-9
show separate views of the emulation mode address map for the 60x processor, a PCI
memory device, and a PCI I/O device, respectively. See Section 7.8, “Emulation Support,”
for more information about emulation mode.
Table 3-7. Emulation Mode Address Map—Processor View
60x Processor Address Range
PCI Address Range
Definition
Hex
Decimal
00000000
0009FFFF
0
640K – 1
No PCI cycle
System memory space
000A0000
000BFFFF
640K
768K – 1
000A0000–000BFFFF
Compatibility hole
1
000C0000
3FFFFFFF
768K
1G – 1
No PCI cycle
System memory space
40000000
7FFFFFFF
1G
2G – 1
No PCI cycle
Reserved
2
80000000
FCFFFFFF
2G
4G – 48M – 1
80000000–FCFFFFFF
PCI memory space
FD000000
FDFFFFFF
4G – 48M
4G – 32M – 1
00000000–00FFFFFF
PCI/ISA memory space
3
FE000000
FE7FFFFF
4G – 32M
4G – 24M – 1
00000000–0000FFFF
PCI/ISA I/O space
(64 Kbytes or 8 Mbytes)
4
FE800000
FEBFFFFF
4G – 24M
4G – 20M – 1
00800000–00BFFFFF
PCI I/O space
5
FEC00000
FEDFFFFF
4G – 20M
4G – 18M – 1
CONFIG_ADDR
PCI configuration
address register
6
FEE00000
FEEFFFFF
4G – 18M
4G – 17M – 1
CONFIG_DATA
PCI configuration data
register
7
FEF00000
FEFFFFFF
4G – 17M
4G – 16M – 1
FEF00000–FEFFFFFF
PCI interrupt
acknowledge
8
FF000000
FF7FFFFF
4G – 16M
4G – 8M – 1
FF000000–FF7FFFFF
64-bit system ROM
space
9
FF800000
FFFFFFFF
4G – 8M
4G – 1
FF800000–FFFFFFFF
8- or 64-bit system ROM
space
9