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2-8
MPC7400 RISC Microprocessor Users Manual
The MPC7400 Processor Register Set
Miscellaneous registers
D Time base (TB). The TB is a 64-bit structure provided for maintaining the
time of day and operating interval timers. The TB consists of two 32-bit
registerstime base upper (TBU) and time base lower (TBL). The time base
registers can be written to only by supervisor-level software, but can be read
by both user- and supervisor-level software. See òTime Base Facility
(TB)OEA,ó in Chapter 2, òPowerPC Register Set,ó of
The Programming
Environments Manual
for more information.
D Decrementer register (DEC). This register is a 32-bit decrementer counter that
provides a mechanism for causing a decrementer exception after a
programmable delay; the frequency is a subdivision of the processor clock.
See òDecrementer Register (DEC),ó in Chapter 2, òPowerPC Register Set,ó of
The Programming Environments Manual
for more information.
Implementation Note
In the MPC7400, the decrementer register is
decremented and the time base increments at a speed that is one-fourth the
speed of the system bus clock.
D Data address breakpoint register (DABR)This optional register is used to
cause a breakpoint exception if a speciTed data address is encountered. See
òData Address Breakpoint Register (DABR),ó in Chapter 2, òPowerPC
Register Set,ó of
The Programming Environments Manual
.
D External access register (EAR). This optional register is used in conjunction
with
eciwx
and
ecowx
. Note that the EAR register and the
eciwx
and
ecowx
instructions are optional in the PowerPC architecture and may not be
supported in all PowerPC processors that implement the OEA. See òExternal
Access Register (EAR),ó in Chapter 2, òPowerPC Register Set,ó of
The
Programming Environments Manual
for more information.
Table 2-2. Additional SRR1 Bits
Bits
Name
Description
1
ICERR
Instruction Cache error
2
DCERR
Data Cache error
3
L2ERR
L2 Tag error
4
TLBERR
TLB array error
5
BRERR
BHT/BTIC array error
10
OTHERR
Other Internal Error
11
L2DP
Set by a data parity error on the L2 bus.
12
MCPIN
Set by the assertion of MCP
13
TEA
Set by a TEA assertion on the 60x bus
14
DP
Set by a data parity error on the 60x bus
15
AP
Set by an address parity error on the 60x bus