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參數(shù)資料
| 型號： | MPC7410RX500LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 885K |
| 代理商： | MPC7410RX500LX |
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18
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.4 L2 Bus AC Specifications
Table 11 provides the L2 bus interface AC timing specifications for the MPC7410 as defined in Figure 8
and Figure 9 for the loading conditions described in Figure 10.
Table 11. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (See Table 3)
Parameter
Symbol
400, 450, 500 MHz
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
tL2CR & tL2CF
—1.0
ns
1
Setup Times: Data and parity
tDVL2CH
1.5
—
ns
2
Input Hold Times: Data and parity
tDXL2CH
—0.0
ns
2
Valid Times:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOV
—
2.5
2.9
3.5
ns
3, 4
Output Hold Times
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOX
0.4
0.8
1.2
1.6
—
ns
3
L2SYNC_IN to high impedance:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOZ
—
2.0
2.5
3.0
3.5
ns
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVdd.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-ohm load (See Figure 10).
4.The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15]
= 10 is recommended.
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