參數(shù)資料
型號(hào)： MPC7410RX500LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 26/44頁(yè)
文件大?。?/td> 885K
代理商： MPC7410RX500LX
32
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Figure 19. Example Voltage Sequencing Circuit
1.8.4 Decoupling Recommendations
Due to the MPC7410 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7410 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7410 system, and the MPC7410 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
Vdd, OVdd, and L2OVdd pin of the MPC7410. It is also recommended that these decoupling capacitors
receive their power from separate Vdd, (L2)OVdd, and GND power planes in the PCB, utilizing short traces
to minimize inductance.
These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd, L2OVdd, and OVdd planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.8.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, L2OVdd, and GND pins of the
MPC7410.
See Section 1.4.2.3, “L2 Clock AC Specifications” for a discussion of the L2SYNC_OUT and L2SYNC_IN
signals.
1.8.6 Output Buffer DC Impedance
The MPC7410 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure
Z0, an external resistor is connected from the chip pad to OVdd or GND. Then, the value of each resistor is
varied until the pad voltage is OVdd/2 (see Figure 20).
2.5 V
1.8 V
MUR420
1N5820
MUR420
1N5820
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