參數(shù)資料
型號: MPC7410RX500LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 34/44頁
文件大?。?/td> 885K
代理商: MPC7410RX500LX
4
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— 8-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction flow changes
Fixed Point Units (FXUs) that share 32 GPRs for integer operands
— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
3-stage floating-point unit and a 32-entry FPR file
— Support for IEEE-754 standard single and double-precision floating-point arithmetic
— 3-cycle latency, 1-cycle throughput (single- or double-precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
AltiVec Unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the
vector complex integer unit (VCIU), and the vector floating-point unit (VFPU).
— Fully pipelined
Load/store unit
— 1-cycle load or store cache access (byte, half word, word, double-word)
— 2-cycle load latency with 1-cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double-word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
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