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參數(shù)資料
| 型號(hào)： | MPC7410RX500LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 6/44頁 |
| 文件大?。?/td> | 885K |
| 代理商： | MPC7410RX500LX |
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14
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 4 provides the AC test load for the MPC7410.
Figure 4. AC Test Load
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to
the midpoint of the signal in question. All output timings assume a purely resistive 50-ohm load (See Figure 4).
Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and
connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid
state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV
symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold
time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)—
note the position of the reference and its state for inputs—and output hold time can be read as the time from the
rising edge (KH) until the output went invalid (OX).
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).
4. This specification is for configuration mode select only. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3].
7. All other output signals are composed of the following— A[0:31], AP[0:3], TT[0:4], TS, TBST, TSIZ[0:2], GBL, WT,
CI,DH[0:31], DL[0:31], DP[0:7],BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.
8. Output valid time is measured from 2.4 V to 0.8 V which may be longer than the time required to discharge from
Vdd to 0.8 V.
9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are
asserted low then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width
for ABB or DBB is 0.5
× t
SYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master
asserting ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold
timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is
guaranteed by design.
10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period
immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it
low. Any master asserting it low in the first clock following AACK will then go to high-Z for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 tsysclk; i.e., it should be high-Z as shown in Figure 6 before the first opportunity for another master to assert
ARTRY. Output valid and output hold timing are tested for the signal asserted. Output valid time is tested for
precharge.The high-Z behavior is guaranteed by design.
11. Guaranteed by design and not tested.
12. Output hold time characteristics can be altered by the use of the L2_TSTCLK pin during system reset, similar to
L2 output hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the
L2_TSTCLK will be included in future revisions of this specification.
Table 9. Processor Bus AC Timing Specifications1 (Continued)
At recommended operating conditions (See Table 3)
Parameter
Symbol2
400, 450, 500 MHz
Unit
Notes
Min
Max
OUTPUT
Z0 = 50
OVdd/2
RL = 50
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| MPC7410THX450NE | 功能描述:微處理器 - MPU NT NITCE RV1.4,1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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