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參數(shù)資料
| 型號： | MPC7410RX500LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 885K |
| 代理商： | MPC7410RX500LX |
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MPC7410 RISC Microprocessor Hardware Specifications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four architecture AltiVec DST streams
Level 1 (L1) cache structure
— 32K, 32-byte line, 8-way set associative instruction cache (iL1)
— 32K, 32-byte line, 8-way set associative data cache (dL1)
— Single-cycle cache access
— Pseudo least recently used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copyback or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruction cache except for ICBI instruction
Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs
— 512K, 1M, and 2Mbyte 2-way set associative L2 cache support
— Copyback or write-through data cache (on a page basis, or for all L2)
— 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size
— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register)
late write synchronous BurstRAMs
— Supports direct mapped mode for 256K, 512K, 1M or 2-Mbyte of SRAM (either all, half, or
none of L2 SRAM must be configured as direct mapped)
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64-bit data bus which also supports 32-bit bus mode
— Selectable interface voltages of 1.8 V and 2.5 V
Memory management unit
— 128-entry, 2-way set associative instruction TLB
— 128-entry, 2-way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (2
52) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
— Snooped and invalidated for TLBI instructions
Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus
— Up to seven outstanding, out-of-order transactions on the bus
— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same
line
— Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e.,
address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).
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相關代理商/技術參數(shù) |
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| MPC7410THX400LE | 功能描述:微處理器 - MPU NT HITCE RV1.4 1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC7410THX400NE | 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360FCCBG - Bulk |
| MPC7410THX450NE | 功能描述:微處理器 - MPU NT NITCE RV1.4,1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC7410THX500LE | 功能描述:微處理器 - MPU NT HITCE RV1.4 1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC7410TRX400NE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
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