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參數(shù)資料
| 型號： | MPC7455 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | MPC7455 |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
47
System Design Information
11111
12.5x
2x
600
(1200)
833
(1666)
938
(1876)
01011
13x
2x
650
(1300)
865
(1730)
975
(1950)
11100
13.5x
2x
675
(1350)
900
(1800)
11001
14x
2x
700
(1400)
933
(1866)
00011
15x
2x
500
(1000)
750
(1500)
1000
(2000)
11011
16x
2x
533
(1066)
800
(1600)
00001
17x
2x
566
(1132)
850
(1900)
00101
18x
2x
600
(1200)
900
(1800)
00111
20x
2x
667
(1334)
1000
(2000)
01001
21x
2x
700
(1400)
01101
24x
2x
800
(1600)
11101
28x
2x
933
(1866)
00110
PLL bypass
PLL off, SYSCLK clocks core circuitry directly
11110
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see
Section 5.2.1,
“Clock AC Specifications
,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup t
IVKH
and hold
time t
IXKH
(see
Table 9
). The result will be that the processor bus frequency will be one-half SYSCLK while the
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note
: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
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