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參數(shù)資料
| 型號： | MPC7455 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 48/64頁 |
| 文件大小： | 1127K |
| 代理商： | MPC7455 |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
48
Freescale Semiconductor
System Design Information
The MPC7455 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7455. The core-to-L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits
of the L3CR register. Generally, the divisor must be chosen according to the frequency supported by the external
RAMs, the frequency of the MPC7455 core, and timing analysis of the circuit board routing.
Table 18
shows various
example L3 clock frequencies that can be obtained for a given set of core frequencies.
9.2 PLL Power Supply Filtering
The AV
DD
power signal is provided on the MPC7455 to provide power to the clock generation PLL. To ensure
stability of the internal clock, the power supplied to the AV
DD
input signal should be filtered of any noise in the 500
kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in
Figure 24
using surface
mount capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AV
DD
pin to minimize noise coupled from nearby circuits.
It is often possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of the 360 CBGA
footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.
Table 18. Sample Core-to-L3 Frequencies
Core Frequency
(MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
500
250
200
167
143
125
100
83
533
266
213
178
152
133
107
89
550
275
220
183
157
138
110
92
600
300
240
200
171
150
120
100
650
2
325
260
217
186
163
130
108
666
2
333
266
222
190
167
133
111
700
2
350
280
233
200
175
140
117
733
2
367
293
244
209
183
147
122
800
2
400
320
266
230
200
160
133
867
2
433
347
289
248
217
173
145
933
2
467
373
311
266
233
187
156
1000
2
500
400
333
285
250
200
166
Notes:
1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some
examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the MPC7455;
see
Section 5.2.3, “L3 Clock AC Specifications,”
for valid L3_CLK frequencies and for more information regarding
the maximum L3 frequency. Shaded cells do not comply with
Table 10
.
2. These core frequencies are not supported by all speed grades; see
Table 8
.
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