- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359188 > MPC7455 (飛思卡爾半導(dǎo)體(中國)有限公司) RISC Microprocessor Hardware Specifications PDF資料下載
參數(shù)資料
| 型號： | MPC7455 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 52/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | MPC7455 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
52
Freescale Semiconductor
System Design Information
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the
input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left
unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also
be disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors.
9.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE
1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible
to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is
also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in
Figure 26
allows the COP port to independently assert HRESET or TRST, while ensuring
that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be
tied to HRESET through a 0-
isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the
COP header be designed into the system as shown in
Figure 26
, if this is not possible, the isolation resistor will allow
future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in
Figure 26
adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100"
centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector
key.
There is no standardized way to number the COP header shown in
Figure 26
; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while
others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with
an IC). Regardless of the numbering, the signal placement recommended in
Figure 26
is common to all known
emulators.
The QACK signal shown in
Figure 26
is usually connected to the PCI bridge chip in a system and is an input to the
MPC7455 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power
mode selection. In order for COP to work, the MPC7455 must see this signal asserted (pulled down). While shown
on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be
populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can
only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is de-asserted
when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC7457 | RISC Microprocessor Hardware Specifications |
| MPC7457EC | RISC Microprocessor Hardware Specifications |
| MPC8241TZQ200C | Intergrated Processor Hardware Specifications |
| MPC8241TZQ266C | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MPC8241TZQ266D | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7457 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7457EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC745BPX300LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BPX350LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BVT300LE | 功能描述:微處理器 - MPU GF REV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。