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參數(shù)資料
| 型號： | MPC745CVT350LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 46/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU HIP4DP 350MHZ 255-PBGA |
| 標準包裝： | 60 |
| 系列： | MPC7xx |
| 處理器類型： | 32-位 MPC7xx PowerPC |
| 速度： | 350MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 255-FCPBGA（21x21） |
| 包裝： | 托盤 |
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
50
Freescale Semiconductor
Document Revision History
9
Document Revision History
Table 19 provides a revision history for this hardware specification.
Table 19. Document Revision History
Revision
Date
Substantive Change(s)
8
2/8/2006
Changed processor descriptor from ‘B’ to ‘C’ for 350 MHz devices and increased power specifications
for full-power mode in Table 7.
7
4/05/2005 Removed phrase “for the ceramic ball grid array (CBGA) package” from Section 8.8; this information
applies to devices in both CBGA and PBGA packages.
Figure 24—updated COP Connector Diagram to recommend a weak pull-up resistor on TCK.
Table 20—added MPC745BPXLE, MPC755BRXLE, MPC755BPXLE, MPC755CVTLE,
MPC755BVTLE and MPC745BVTLE part numbers. These devices are fully addressed by this
document.
Corrected Revision Level in Table 23: Rev E devices are Rev 2.8, not 2.7.
Added MPC755CRX400LE and MPC755CPX400LE to devices supported by this specification in
Table 20.
Removed “Advance Information” from title block on page 1.
6.1
1/21/2005 Updated document template.
6
—
Removed 450 MHz speed grade throughout document. These devices are no longer supported for new
designs; see Section 1.10.2 for more information.
Relaxed voltage sequencing requirements in Notes 3 and 4 of Table 1.
Corrected Note 2 of Table 7.
Changed processor descriptor from ‘B’ to ‘C’ for 400 MHz devices and increased power specifications
for full-power mode in Table 7. XPC755Bxx400LE devices are no longer produced and are documented
in a separate part number specification; see Section 1.10.2 for more information.
Increased power specifications for sleep mode for all speed grades in Table 7.
Removed ‘Sleep Mode (PLL and DLL Disabled)—Typical’ specification from Table 7; this is no longer
tested or characterized.
Added Note 4 to Table 7.
Revised L2 clock duty cycle specification in Table 11 and changed Note 7.
Corrected Note 3 in Table 20.
Replaced Table 21 and added Tables 22 and 23.
5
—
Added Note 6 to Table 10; clarification only as this information is already documented in the MPC750
RISC Microprocessor Family User’s Manual.
Revised Figure 24 and Section 1.8.7.
Corrected Process Identifier for 450 MHz part in Table 20.
Added XPC755BRXnnnTx series to Table 21.
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