參數(shù)資料
型號： MPC8358EZQAGDGA
廠商： Freescale Semiconductor
文件頁數(shù)： 9/95頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 668-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 668-PBGA-PGE（29x29）
包裝： 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
17
RESET Initialization
Table 11 provides the PLL and DLL lock times.
5.3
QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine
block’s communication interfaces.
NOTE
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting the performance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.
Table 12 lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block
core frequency for each interface.
Table 11. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs—
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.
Table 12. QUICC Engine Block Operating Frequency Limitations
Interface
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1 (MHz)
Notes
Ethernet Management: MDC/MDIO
10 (max)
10
20
—
MII
25 (typ)
100
50
—
RMII
50 (typ)
100
50
—
GMII/RGMII/TBI/RTBI
125 (typ)
1000
250
—
SPI (master/slave)
10 (max)
10
20
—
UCC through TDM
50 (max)
70
8
× F2
MCC
25 (max)
16.67
16
× F
2, 4
UTOPIA L2
50 (max)
800
2
× F2
POS-PHY L2
50 (max)
800
2
× F2
HDLC bus
10 (max)
10
20
—
HDLC/transparent
50 (max)
50
8/3
× F2, 3
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MPC8358EZUADDGA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8360E/MPC8358E PowerQUICC II Pro Processor
MPC8358EZUAGDEA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8360E/MPC8358E PowerQUICC II Pro Processor
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