參數(shù)資料
型號: MPC8377EWLANA
廠商: Freescale Semiconductor
文件頁數(shù): 12/127頁
文件大?。?/td> 0K
描述: ACCESS POINT/ROUTER MPC8377
標(biāo)準(zhǔn)包裝: 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
109
This table provides the operating frequencies for the TePBGA II package under recommended operating
conditions (see Table 3).
PCI Express1, 2
csb_clk/3
Off, c
sb_clk, csb_clk/2, csb_clk/3
SATA1, 2
csb_clk/3
Off,
csb_clk
1 This only applies to I2C1 (I2C2 clock is not configurable).
Table 74. Operating Frequencies for TePBGA II
Parameter1
Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
e300 core frequency (
core_clk)
333
800
Coherent system bus frequency (
csb_clk)
133
400
DDR2 memory bus frequency (MCK)1
250
400
DDR1 memory bus frequency (MCK) 2
167
333
Local bus frequency (LCLK
n)1
133
Local bus controller frequency (
lbc_clk)
400
PCI input frequency (CLKIN or PCI_CLK)
25
66
eTSEC frequency
133
400
Security encryption controller frequency
200
USB controller frequency
200
eSDHC controller frequency
200
PCI Express controller frequency
400
SATA controller frequency
200
Notes:
1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting
csb_clk,
MCK, LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,
USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.
2. The DDR data rate is 2
× the DDR memory bus frequency.
3. The local bus frequency is , , or 1/8 of the
lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the
csb_clk frequency (depending on RCWLR[LBCM]).
Table 73. Configurable Clock Units (continued)
Unit
Default Frequency
Options
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