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| 型號： | MPC8377EWLANA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 25/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | ACCESS POINT/ROUTER MPC8377 |
| 標準包裝： | 1 |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
120
Freescale Semiconductor
RθJC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of this
chip.
25.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The AVDD
level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD
through a low frequency filter scheme.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 65, one to each of the five AVDD pins. By
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Figure 65. PLL Power Supply Filter Circuit
25.2
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These
decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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| MPC8377EWLANB | 功能描述:WiFi/802.11模塊 KIT RoHS:否 制造商:Taiyo Yuden 支持協(xié)議:802.11 b/g/n 頻帶: 數(shù)據(jù)速率:150 Mbps 接口類型:SDIO 傳輸功率（最大）: 天線連接器類型: 工作電源電壓:3.4 V to 5.5 V 傳輸供電電流: 接收供電電流: 最大工作溫度:+ 80 C 尺寸:35 mm x 15 mm x 2.9 mm |
| MPC8377EZQAFDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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| MPC8377EZQAFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377EZQAGDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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